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ASAHI KASEI
[AK4569]
AK4569
20-Bit Stereo CODEC with IPGA & HP-AMP
GENERAL DESCRIPTION The AK4569 is a 20bit CODEC with built-in Input PGA and Headphone Amplifier. The AK4569 includes a microphone/line input selector and an ALC circuit for input, and a Mono line output buffer, analog volume controls and stereo headphone amplifier for output. The AK4569 also features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features "pop-free" power-on/off, a mute control and delivers 8.7mW of power into 16 load via 6.8 series resistor. The AK4569 is housed in a 28pin QFN package, making it suitable for portable applications. FEATURE 2ch 20bit ADC - S/N: 89dB - Single-ended input - 2 stereo inputs selector - Analog input PGA: +32dB -19dB, Mute, 0.5dB step (MIC input) +20dB -31dB, Mute, 0.5dB step (LINE input) - Digital HPF for DC-offset cancellation - I/F format: 20bit MSB justified, I2S 2ch 20bit DAC - I/F Format: I2S, 20bit MSB justified, 20bit/16bit LSB justified - Digital ATT: 0dB -127dB, Mute, 0.5dB step (soft transition) - Soft mute - Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz - Bass Boost Function Sampling Rate: 8kHz 48kHz System clock: 256fs/384fs/512fs - Input level: CMOS or 1Vpp Analog Input Analog Mixing Circuit Mono Lineout - Analog volume: 0dB -30dB, Mute, 2dB step Headphone Amplifier - Output Power: 8.7mW x 2ch @16 load & 6.8 series resistor - S/N: 90dB P Interface: 3-wire Power management Power supply: 2.7V 3.6V Power dissipation: 15mA Ta: -40 85C Small Package: 28pin QFN (5.2mm x 5.2mm, 0.5mm pitch)
MS0292-E-01 -1-
2005/07
ASAHI KASEI
[AK4569]
AVDD
DVDD
VREF VCOM
VREF VCOM
IPGA & ADC
AINL1 AINL2 IPGA ADC MCLK HPF BICK Audio I/F Controller LRCK SDTO HP-Amp HPR DAC BOOST DATT
AINR1 AINR2
HP-amp DAC
HPL
SDTI
MOUT
MOUT
Control Register
CSN CCLK CDTI
LIN RIN MIN HVDD HVSS MUTET PDN
AVSS
DVSS
Figure 1. Block diagram
MS0292-E-01 -2-
2005/07
ASAHI KASEI
[AK4569]
Ordering Guide
AK4569VN AKD4569 -40 +85C 28pin QFN (0.5mm pitch) Evaluation board for AK4569
Pin Layout
AVDD
AVSS 23
28
25
27
PDN CSN CCLK CDTI LRCK MCLK BICK
1 2 3 4 5 6 7 10 12 13 14 8 9 11 Top View
26
24
22 21 20 19 18 17 16 15
VCOM
AINR1
AINR2
AINL1
AINL2
VREF LIN RIN MIN MOUT MUTET HPL
DVDD
HVDD
SDTO
DVSS
HVSS
SDTI
Comparison Table between AK4566 and AK4569
Function DAC Digital Filter Stopband Attenuation (min) Passband Ripple (max) Frequency Response including Analog Filter (0 20.0kHz) The condition to stop the external clocks. AK4566 43dB 0.06dB 0.5dB PDN pin = "L" AK4569 59dB 0.01dB 1.0dB PDN pin = "L" or PMADC=PMDAC bits = "0"
MS0292-E-01 -3-
HPR
2005/07
ASAHI KASEI
[AK4569]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name PDN CSN CCLK CDTI LRCK MCLK BICK SDTI SDTO DVDD DVSS HVSS HVDD HPR HPL MUTET MOUT MIN RIN LIN VREF I/O I I I I I I I I O O O O O I I I O Function Power-down Pin When "L", the AK4569 is in power-down mode and is held in reset. The AK4569 should always be reset upon power-up. Control Data Chip Select Pin Control Clock Input Pin Control Data Input Pin L/R Clock Pin This clock determines which audio channel is currently being output on SDTO pin and input on SDTI pin. Master Clock Input Pin Serial Bit Clock Pin This clock is used to latch audio data. Audio Data Input Pin Audio Data Output Pin SDTO pin goes to DVSS when PDN pin is "L". Digital Power Supply Pin Digital Ground Pin Ground Pin for Headphone Amplifier Power Supply Pin for Headphone Amplifier Rch Headphone Amplifier Output Pin HPR pin goes to HVSS when PDN pin is "L". Lch Headphone Amplifier Output Pin HPL pin goes to HVSS when PDN pin is "L". Mute Time Constant Control Pin A capacitor for mute time constant should be connected between MUTET pin and HVSS pin. MUTET pin goes to HVSS when PDN pin is "L". Mono Analog Output Pin MOUT pin goes to Hi-Z when PDN pin is "L". Mono Analog Input Pin Rch Analog Input Pin Lch Analog Input Pin Reference Voltage Output Pin, 2.1V (typ, respect to AVSS) Normally connected to AVSS pin with 0.1F ceramic capacitor in parallel with a 4.7F electrolytic capacitor. VREF pin goes to AVSS when PDN pin is "L". Common Voltage Output Pin, 1.25V (typ, respect to AVSS) Normally connected to AVSS pin with 0.1F ceramic capacitor in parallel with a 2.2F electrolytic capacitor. VCOM pin goes to AVSS when PDN pin is "L". Analog Ground Pin Analog Power Supply Pin Rch Analog Input 2 Pin for ADC (MIC Input) Lch Analog Input 2 Pin for ADC (MIC Input) Rch Analog Input 1 Pin for ADC (LINE Input) Lch Analog Input 1 Pin for ADC (LINE Input)
22 23 24 25 26 27 28
VCOM AVSS AVDD AINR2 AINL2 AINR1 AINL1
O I I I I
Note: No digital input pins must be left floating.
MS0292-E-01 -4-
2005/07
ASAHI KASEI
[AK4569]
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name HPR, HPL, MOUT, AINR2, AINL2, AINR1, AINL1 SDTO SDTI Setting These pins should be open. This pin should be open. This pin should be connected to DVSS.
ABSOLUATE MAXIMUM RATING (AVSS, DVSS, HVSS=0V; Note 1) Parameter Symbol min max Power Supplies Analog AVDD -0.3 4.6 DVDD 4.6 Digital -0.3 HVDD 4.6 HP-AMP -0.3 GND1 0.3 |AVSS - HVSS| (Note 2) 0.3 |AVSS - DVSS| (Note 2) GND2 Input Current (any pins except for supplies) IIN 10 Analog Input Voltage (Note 3) VINA (AVDD+0.3) or 4.6 -0.3 Digital Input Voltage (Note 4) VIND (DVDD+0.3) or 4.6 -0.3 Ambient Temperature Ta 85 -40 Storage Temperature Tstg 150 -65 Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS and HVSS must be connected to the same analog ground plane. Note 3. MIN, RIN, LIN, AINR2, AINL2, AINR1, AINL1 pins. Max is smaller value between (AVDD+0.3) and 4.6V. Note 4. PDN, CSN, CCLK, CDTI, LRCK, MCLK, BICK, SDTI pins. Max is smaller value between (DVDD+0.3) and 4.6V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Units V V V V V mA V V C C
RECOMMEND OPERATING CONDITIONS (AVSS, DVSS, HVSS=0V; Note 1) Parameter Symbol min typ max Units 2.5 Power Supplies Analog V 3.6 3.0 AVDD V 3.6 or (AVDD+0.3) 3.0 DVDD 2.5 or (AVDD-0.3) Digital (Note 5) V 3.6 3.0 HVDD HP-AMP 2.5 Note 1. All voltages with respect to ground. Note 5. Min is larger value between 2.5V and (AVDD-0.3). Max is smaller value between 3.6V and (AVDD+0.3).
* AKM assumes no responsibility for usage beyond the conditions in this datasheet.
MS0292-E-01 -5-
2005/07
ASAHI KASEI
[AK4569]
ANALOG CHARACTERISTICS (Ta=25C; AVDD=DVDD=HVDD=3.0V, AVSS =DVSS=HVSS=0V; fs=44.1kHz; BOOST OFF; Signal Frequency =1kHz; Measurement band width=20Hz 20kHz; unless otherwise specified) Parameter min Typ max Units 20 bit ADC Resolution IPGA Characteristics: (AINL1, AINR1 pins) (LINE IN) Input Voltage 1.35 1.5 1.65 Vpp Input Resistance 25 50 75 k Step Size 0.1 0.5 0.9 dB Gain Control Range +20 dB -31 IPGA Characteristics: (AINL2, AINR2 pins) (MIC IN) Input Voltage 1.35 1.5 1.65 Vpp Input Resistance 6 12.5 19 k Step Size 0.1 0.5 0.9 dB Gain Control Range +32 dB -19 (Note 6) ADC Characteristics: 74 84 dB S/(N+D) (-1dB Input) 82 89 dB D-Range (-60dB Input, A-weighted)) S/N (A-weighted) 82 89 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.2 0.5 dB Power Supply Rejection (Note 11) 50 dB 20 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 7) Load impedance is a serial connection with RL =22.8 and CL=100F. S/(N+D) (0dBFS Output) 50 70 dB 82 90 dB D-Range (-60dBFS Output, A-weighted) S/N (A-weighted) 82 90 dB Interchannel Isolation 70 90 dB Interchannel Gain Mismatch 0.2 0.5 dB Load Resistance (Note 8) 20 Load Capacitance (C1 in Figure 2) 30 pF (C2 in Figure 2) (Note 9) 300 pF Output Voltage 1.35 1.5 1.65 Vpp Power Supply Rejection (Note 11) 50 dB (Note 10) Mono Output: (MOUT pin) S/(N+D) (0dBFS Output) 70 84 dB S/N (A-weighted) 82 90 dB Load Resistance (Note 8) 10 k Load Capacitance 30 pF Output Voltage 1.35 1.5 1.65 Vpp Power Supply Rejection (Note 11) 50 dB Output Volume: (MOUT pin) Step Size 1 2 3 dB Gain Control Range 0 dB -30 Note 6. The signal inputs are AINL1/AINR1 or AINL2/AINR2. The value of the IPGA is set to 0dB. On-chip HPF cancels the IPGA and ADC offsets. Note 7. DACL=DACR= "1", MINL=MINR=LIN=RIN= "0", and ATTL=ATTR=0dB. Note 8. AC Load Note 9. A resistor greater than 6.8 is inserted in series. Note 10. DACM= "1", LINM=RINM=MINM= "0", ATTL=ATTR=ATTM=0dB, and common mode signal is input to L/Rch of DAC. Note 11. PSR is applied to AVDD, DVDD and HVDD with 1kHz, 50mVpp.
MS0292-E-01 -6-
2005/07
ASAHI KASEI
[AK4569]
Parameter min typ max Units Analog Input: (LIN/RIN/MIN pins) Input Resistance 25 50 75 k Gain dB -5 -6 -7 LIN/RINMOUT dB +1 0 -1 MINMOUT, LIN/MINHPL, RIN/MINHPR Power Supplies Power Supply Current Normal Operation (PDN= "H") mA 24 15 AVDD + DVDD + HVDD (Note 12) Power-Down Mode (PDN= "L") 100 1 AVDD + DVDD + HVDD (Note 13) A Note 12. All blocks are powered-up (PMVCM=PMADC=PMDAC=PMHPL=PMHPR=PMMO= "1"), and HP-Amp output is off. AVDD=9mA(typ), DVDD=3mA(typ), HVDD=3mA(typ). 9mA(typ) at playback only (PMVCM=PMDAC=PMHPL=PMHPR=PMMO= "1", PMADC= "0"). AVDD=4mA(typ), DVDD=2mA(typ), HVDD=3mA(typ). Note 13. All digital input pins including clock pins (MCLK, BICK and LRCK) are held at DVDD or DVSS. PDN pin is held at DVSS.
HP-Amp
HPL, HPR > 6.8 C1 100uF
+
+
C2 16
Figure 2. Headphone amp output circuit
MS0292-E-01 -7-
2005/07
ASAHI KASEI
[AK4569]
FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD=2.5 3.6V; fs=44.1kHz; DEM=OFF; BOOST=OFF) Parameter Symbol min typ max Units ADC Digital Filter (LPF): PB 0 17.4 kHz Passband (Note 15) 0.1dB 20.0 kHz -1.0dB 21.1 kHz -3.0dB Stopband (Note 15) SB 25.7 kHz Passband Ripple PR dB 0.1 Stopband Attenuation SA 65 dB Group Delay (Note 16) GD 17.0 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): Frequency Response (Note 15) -3dB FR 3.4 Hz 10 Hz -0.5dB 22 Hz -0.1dB DAC Digital Filter: (Note 14) Passband (Note 15) 0.1dB PB 0 19.6 kHz 20.0 kHz -0.7dB 22.05 kHz -6.0dB Stopband (Note 15) SB 25.2 kHz Passband Ripple PR dB 0.01 Stopband Attenuation SA 59 dB Group Delay (Note 16) GD 16.8 1/fs Group Delay Distortion 0 GD s DAC Digital Filter + Analog Filter: (Note 14)(Note 17) FR dB Frequency Response 0 20.0kHz 1.0 BOOST Filter: (Note 17) (Note 18) dB FR 20Hz Frequency Response 5.74 dB 100Hz MIN 2.92 dB 1kHz 0 dB FR 20Hz 5.94 dB 100Hz MID 4.71 dB 1kHz 0.14 20Hz FR dB 16.04 dB MAX 100Hz 10.55 1kHz dB 0.3 Note 14. BOOST OFF (BST1-0 = "00") Note 15. The passband and stopband frequencies scale with fs. For example (DAC), PB=0.44*fs(@0.1dB), SB=0.57*fs(@-59dB). Note 16. This is the calculated delay time caused by digital filtering. This time is measured from the input of analog signal to setting the 20 bit data of both channels on input register to the output register of ADC. This time also includes group delay of HPF. For DAC, this time is from setting the 20 bit data of both channels on input register to the output of analog signal. Note 17. DACL HPL, DACR HPR, DACL/R MOUT. Note 18. These frequency responses scale with fs. If high-level signal is input, the AK4569 clips at low frequency.
MS0292-E-01 -8-
2005/07
ASAHI KASEI
[AK4569]
Boost Frequency (fs=44.1kHz) 0 Output Level [dB] -5 -10 -15 -20 -25 0.01 0.1 Frequency [kHz] 1 10
MIN MID
MAX
Figure 3. Boost Frequency (fs=44.1kHz)
DC CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD = 2.5 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL Input Voltage at AC Coupling (Note 19) VAC 1.0 VOH DVDD-0.4 High-Level Output Voltage (Iout = -100A) VOL Low-Level Output Voltage (Iout = 100A) Input Leakage Current Iin Note 19. When AC coupled capacitor is connected to MCLK pin.
typ
max 30%DVDD 0.4 10
-
Units V V Vpp V V A
MS0292-E-01 -9-
2005/07
ASAHI KASEI
[AK4569]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD, HVDD = 2.5 3.6V: CL = 20pF) Parameter Symbol min typ max Units Master Clock Timing MHz 2.048 24.576 fCLK Frequency ns 0.4/fCLK tCLKL Pulse Width Low (Note 20) ns 0.4/fCLK tCLKH Pulse Width High (Note 20) ns 0.4/fCLK tACW AC Pulse Width (Note 21) LRCK Timing kHz 44.1 48 8 fs Frequency % 55 45 Duty Duty Cycle Serial Interface Timing (Note 22) ns 325.5 tBCK BICK Period ns 130 tBCKL BICK Pulse Width Low ns 130 tBCKH Pulse Width High ns 50 tLRB LRCK Edge to BICK "" (Note 23) ns 50 tBLR BICK "" to LRCK Edge (Note 23) ns 80 tLRS LRCK to SDTO(MSB) ns 80 tBSD BICK "" to SDTO ns 50 tSDH SDTI Hold Time ns 50 tSDS SDTI Setup Time Control Interface Timing ns 200 tCCK CCLK Period ns 80 tCCKL CCLK Pulse Width Low ns 80 tCCKH Pulse Width High ns 40 tCDS CDTI Setup Time ns 40 tCDH CDTI Hold Time ns 150 tCSW CSN "H" Time ns 50 tCSS CSN "" to CCLK "" ns 50 tCSH CCLK "" to CSN "" Power-down & Reset Timing tPD 150 ns PDN Pulse Width (Note 24) tPDV 2081 1/fs PMADC "" to SDTO valid (Note 25) Note 20. Except AC coupling. Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 4.) Note 22. Refer to "Serial Data Interface". Note 23. BICK rising edge must not occur at the same time as LRCK edge. Note 24. The AK4569 can be reset by bringing PDN= "L" to "H" only upon power up. Note 25. This is the count of LRCK "" from PMADC bit="1".
MS0292-E-01 - 10 -
2005/07
ASAHI KASEI
[AK4569]
Timing Diagram
1/fCLK
1000pF MCLK Input 100k AVSS Measurement Point AVSS
tACW
tACW
Figure 4. MCLK AC Coupling Timing
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Figure 5. Clock Timing
MS0292-E-01 - 11 -
2005/07
ASAHI KASEI
[AK4569]
LRCK tBLR tLRB
VIH VIL
BICK
VIH VIL tLRS tBSD
SDTO tSDS
50%DVDD
tSDH VIH VIL
SDTI
Figure 6. Serial Interface Timing
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
Figure 7. WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
Figure 8. WRITE Data Input Timing
MS0292-E-01 - 12 -
2005/07
ASAHI KASEI
[AK4569]
VIH CSN VIL tPDV
SDTO
50%DVDD
tPD PDN VIL
Figure 9. Power-down & Reset Timing
MS0292-E-01 - 13 -
2005/07
ASAHI KASEI
[AK4569]
OPERATION OVERVIEW System Clock
The external clocks required to operate the AK4569 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 1 shows system clock example. LRCK fs 8kHz 11.025kHz 12kHz 16kHz 22.05kHz 24kHz 32kHz 44.1kHz 48kHz MCLK (MHz) 384fs 3.072 4.2336 4.608 6.144 8.4672 9.216 12.288 16.9344 18.432 BICK (MHz) 64fs 0.512 0.7056 0.768 1.024 1.4112 1.536 2.048 2.8224 3.072
256fs 2.048 2.8224 3.072 4.096 5.6448 6.144 8.192 11.2896 12.288
512fs 4.096 5.6448 6.144 8.192 11.2896 12.288 16.384 22.5792 24.576
Table 1. System Clock Example
External clocks (MCLK, BICK and LRCK) are needed to operate ADC or DAC. All external clocks (MCLK, BICK and LRCK) should always be present whenever the ADC or DAC is in normal operation mode (PMADC bit = "1" or PMDAC bit = "1"). If these clocks are not provided, the AK4569 may draw excess current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, AK4569 should be placed in power-down mode (PDN pin = "L" or PMADC bit = PMDAC bit = "0"). When MCLK is input with AC coupling, the MCKAC bit should be set to "1". If MCLK with AC coupling stops, MCKPD bit should be set to "1". For low sampling rates, outband noise causes both DR and S/N to degrade. DR and S/N are improved by setting DFS bit to "1". Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS bit is "1", MCLK needs 512fs. During normal operation, when the ADC or DAC sampling frequency is changed (PMADC bit = "1" or PMDAC bit = "1"), the DAC output should be soft-muted or "0" data should be input to avoid pop noise. DFS 0 1 fs 8kHz48kHz 8kHz24kHz MCLK 256fs/384fs/512fs 512fs S/N (fs=8kHz, A-weighted) HP-amp MOUT 84dB 84dB 90dB 88dB
Default
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
MS0292-E-01 - 14 -
2005/07
ASAHI KASEI
[AK4569]
Serial Data Interface
The AK4569 interfaces with external systems via the BICK, LRCK, SDTO and SDTI pins. Four data formats are available and are selected by setting DIF1 and DIF0 bits (Table 3). Mode 0 of SDTI is compatible with existing 16bit DACs and digital filters. Mode 1 of SDTI is a 20bit version of Mode 0. Mode 2 of SDTI is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In SDTI Modes 2 and 3, the following formats are also valid: 16-bit data followed by four zeros and 18-bit data followed by two zeros. In all modes, the serial data is MSB first and 2's complement format. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO 20bit, MSB justified 20bit, MSB justified 20bit, MSB justified IIS (I2S) SDTI 16bit, LSB justified 20bit, LSB justified 20bit, MSB justified IIS (I2S) BICK 32fs 40fs 40fs 32fs or 40fs LRCK H/L H/L H/L L/H
Default
Table 3. Audio Data Format
LRCK
0 1 2 16 17 18 19 20 21 31 0 1 2 16 17 18 19 20 21 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
19 18 4 3 2 1 0 19 18 4 3 2 1 0 19
Don't Care
15 14 13
12
11
1
0
Don't Care
15 14 13
12
11
1
0
0
1
2
8
9
10
11
12
13
14
15
0
1
2
8
9
10
11
12
13
14
15
0
1
BICK(32fs) SDTO(o) SDTI(i)
19 18 12 11 10 9 8 7 6 5 4 19 18 12 11 10 9 8 7 6 5 4 19
15 14
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
15
Lch Data
Rch Data
Figure 10. Mode 0 Timing
LRCK
0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 1
BICK(64fs) SDTO(o) SDTI(i)
19 18 8 7 6 0 19 18 8 7 6 0 19
Don't Care
19 18
12
11
1
0
Don't Care
19 18
12
11
1
0
Lch Data
Rch Data
Figure 11. Mode 1 Timing
MS0292-E-01 - 15 -
2005/07
ASAHI KASEI
[AK4569]
LRCK
0 1 2 15 16 17 18 19 20 30 31 0 1 2 15 16 17 18 19 20 30 31 0 1
BICK(64fs) SDTO(o) SDTI(i) 16bit SDTI(i) 18bit SDTI(i) 20bit
19 18 4 3 2 1 0 19 18 4 3 2 1 0 19
15 14
0
Don't Care
1 0
15 14
0
Don't Care
1 0
15
17 16
2
Don't Care
1 0
17 16
2
Don't Care
1 0
17
19 18
4
3
2
Don't Care
19 18
4
3
2
Don't Care
19
Lch Data
Rch Data
Figure 12. Mode 2 Timing
LRCK
0 1 2 3 16 17 18 19 20 21 30 31 0 1 2 3 16 17 18 19 20 21 30 31 0 1
BICK(64fs) SDTO(o) SDTI(i) 16bit SDTI(i) 18bit SDTI(i) 20bit
0 1
19 18
4
3
2
1
0
19 18
4
3
2
1
0
15 14
0
Don't Care
1 0
15 14
0
Don't Care
1 0
17 16
2
Don't Care
1 0
17 16
2
Don't Care
1 0
19 18
4
3
2
Don't Care
19 18
4
3
2
Don't Care
2
3
8
9
10
11
12
13
14
15
0
1
2
3
8
9
10
11
12
13
14
15
0
1
BICK(32fs) SDTO(o) SDTI(i)
4 19 18 12 11 10 9 8 7 6 5 4 19 18 12 11 10 9 8 7 6 5 4
0
15 14
8
7
6
5
4
3
2
1
0
15 14
8
7
6
5
4
3
2
1
0
Lch Data
Rch Data
Figure 13. Mode 3 Timing
Digital High Pass Filter
The AK4569 has a Digital High Pass Filter (HPF) to cancel DC-offsets in the ADC and IPGA. The cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This filter scales with the sampling frequency (fs).
MS0292-E-01 - 16 -
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ASAHI KASEI
[AK4569]
ALC Operation
[1] ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds ALC limiter detection level (LMTH), IPGA value is attenuated by ALC limiter ATT step (LMAT1-0) automatically. The IPGA is then set to the same value for both channels. When ZELMN = "1", the timeout period is set by LTM1-0 bits. The attenuation operation is done continuously until the input signal level becomes LMTH or less. After finishing the attenuation operation, if ALC bit does not change to "0", the operation repeats when the input signal level exceeds LMTH. When ZELMN = "0", the ALC limiter operation is attenuated by the ZTM1-0 bits setting. The IPGA value is automatically attenuated using zero crossing detection. The ALC operation of the AK4569 corresponds to the impulse noise. If the impulse noise is supplied at ZELMN = "0", the ALC limiter operation becomes faster period than a set of ZTM1-0 bits. In case of ZELMN = "1", it becomes the same period as LTM1-0 bits. [2] ALC Recovery Operation The ALC recovery operation waits for the WTM1-0 bits to be set after completing the ALC limiter. If the input signal does not exceed "ALC recovery waiting counter reset level (LMTH)", the ALC recovery operation is done. The IPGA value is automatically incremented by this operation up to the set reference level (REF6-0) with zero crossing detection which timeout period is set by ZTM1-0 bits. Then the IPGA value is set for both Lch and Rch. The ALC recovery operation is done at a period set by WTM1-0 bits. When zero cross is detected at the IPGA output during the wait period set by WTM1-0 bits, the ALC recovery operation waits until WTM1-0 period and the next recovery operation is done. During the ALC recovery operation or the recovery waiting, when either input signal level of Lch or Rch in IPGA exceeds the ALC limiter detection level (LMTH), the ALC recovery operation changes into the ALC limiter operation immediately. When (ALC recovery waiting counter reset level: LMTH) (IPGA output level) < (ALC limiter detection level: LMTH) during the ALC recovery operation, the ALC recovery operation wait timer is reset. Therefore, when (ALC recovery waiting counter reset level: LMTH) > (IPGA output level), the ALC recovery operation wait timer starts. The ALC operation of the AK4569 corresponds to the impulse noise. If the impulse noise is supplied, the ALC recovery operation becomes faster period than a set of ZTM1-0 or WTM1-0 bits. Others: When either channel enters the limiter operation while waiting time for a zero crossing, the present ALC recovery operation stops, according as the small value of IPGA (a channel waiting zero crossing), the ALC limiter operation is done. When both channels are waiting for the next ALC recovery operation, the ALC limiter operation is done from the IPGA value of a point in time. ZTM1-0 bits set zero crossing timeout and WTM1-0 bits set the ALC recovery operation period. When the ALC recovery waiting time (WTM1-0 bits) is shorter than zero crossing timeout period (ZTM1-0 bits), the ALC recovery is operated by the zero crossing timeout period. Therefore, in this case, the ALC recovery operation period is not constant.
MS0292-E-01 - 17 -
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ASAHI KASEI
[AK4569]
[3] ALC Operation Example The following registers should not be changed during the ALC operation: LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELMN.
Manual mode
WR (Power Management Control & Signal Select)
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (LMAT1-0, RATT, LMTH)
WR (REF6-0) * The value of IPGA should be the same or smaller than REF's.
WR (IPGA6-0)
WR (ALC= "1",ZELMN)
ALC Operation
No
Finish ALC mode?
Yes WR (ALC="0")
Finish ALC mode and return to Manual mode
Figure 14. Registers set-up sequence at ALC operation (WR=Write)
MS0292-E-01 - 18 -
2005/07
ASAHI KASEI
[AK4569]
IPGA Operation
[Write Operation at ALC Enabled] The values of IPGA6-0 bits are ignored during ALC operation. [Write Operation at ALC Disabled] Channel independent zero crossing detection is used. If there are no zero crossings, then the level will change after a timeout. The ZTM1-0 bits set the zero crossing timeout. When a P writes to the IPGA6-0 bits, the zero crossing counter is reset and starts. When the IPGA output signal detects zero crossing or a zero crossing timeout, the written value from the P becomes valid. When writing to the IPGA6-0 bits continually, the control register should be written by an interval more than zero crossing timeout. If not, there is a possibility that each IPGA of L/R channels has a different gain. [IPGA Gain after completing ALC operation] The IPGA6-0 bits are not updated by the actual gain of IPGA changed during ALC operation. In order to set the actual gain of IPGA with the IPGA6-0 bits, the IPGA6-0 bits should be written after zero crossing timeout period when completing ALC operation (ALC bit= "1" "0").
MS0292-E-01 - 19 -
2005/07
ASAHI KASEI
[AK4569]
Digital Attenuator
The AK4569 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to -127dB or MUTE) for each channel (Table 19). At DATTC= "1", ATTL7-0 bits control both Lch and Rch attenuation levels. At DATTC= "0", ATTL7-0 bits control the Lch level and ATTR7-0 bits control the Rch level. The ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 15). When ATS= "0", a soft transition between the set values occurs(1062 levels). It takes 1061/fs (24ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is "0". When the PMDAC returns to "1", the ATTs fade to their current value. Digital attenuator is independent of the soft mute function.
Soft Mute
Soft mute operation is performed in the digital domain. When SMUTE bit goes to "1", the output signal is attenuated by - ("0") via the cycle set by TM1-0 bit (Table 18). When SMUTE bit returns to "0", the mute is cancelled and the output attenuation gradually changes to 0dB via the cycle set by TM1-0 bits. If the soft mute is cancelled within the cycle set by TM1-0 bits after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit TM1-0 bit 0dB Attenuation (1) (3) TM1-0 bit
-
GD (2) Analog Output GD
Figure 15. Soft Mute Function NOTE: (1) The output signal is attenuated until - ("0") by the cycle set by TM1-0 bits. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by TM1-0 bits, the attenuation is discontinued and returned to 0dB(the setting value).
MS0292-E-01 - 20 -
2005/07
ASAHI KASEI
[AK4569]
De-emphasis Filter
The AK4569 includes a digital de-emphasis filter (tc = 50/15s) by IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 16).
Bass Boost Function
By controlling BST1-0 bits, the low frequency boost signal can be output from DAC. The setting value is common in Lch and Rch (Table 17). The cut-off frequency (fc) of HPF depends on the external resistor and capacitor values. Table 4 shows the relationship of external resistor, capacitor, fc and output power, where load resistance of headphone is 16. Output level of headphone amp is 1.5Vpp (typ).
HP-AMP
R
C
Headphone 16
AK4569
Figure 16. External Circuit Example of Headphone R [] fc [Hz] fc [Hz] Output Power [mW] BOOST=OFF BOOST=MID 47 148.6 65 6.8 8.7 100 69.8 27 47 105.8 43 16 4.4 100 49.7 20 Table 4. Relationship of external circuit, output power and frequency response C [F] Note: Cut-off frequency (fc) at BOOST=MID is approximate value.
System Reset
The AK4569 should be reset once by bringing PDN "L" upon power-up. After exiting reset, VCOM, IPGA, ADC, DAC, HPL, HPR and MOUT switch to the power-down state. The contents of the control register are maintained until the reset is done. ADC exits reset and power down state by MCLK after PMADC bit is changed to "1", and then ADC is powered up and the internal timing starts clocking by LRCK "". ADC is in the power-down mode until MCLK and LRCK are input. DAC also exits reset and power down state when MCLK and LRCK are input after PMDAC= "1".
MS0292-E-01 - 21 -
2005/07
ASAHI KASEI
[AK4569]
Power-Up/Down Sequence
1) ADC
Power Supply (1) >150ns PDN pin HPLMT, HPRMT bit PMVCM bit (4) Clock Input PMADC bit Don't care (3) >0 (2) >0 Don't care
(6) 2081/fs Init Cycle Normal Operation PD (Hi-Z) (7) GD (7) GD
(6) 2081/fs Init Cycle Normal Operation
ADC Internal State
PD(Power-down) (5)
AIN pin SDTO pin
(Hi-Z)
(7) GD
Figure 17. Power-up/down sequence of ADC PDN pin should be set to "H" at least 150ns after the power is supplied. HPLMT, HPRMT and PMVCM bits should be changed to "1" after PDN pin goes to "H". PMADC bit should be changed to "1" after HPLMT, HPRMT and PMVCM bits are changed to "1". External clocks (MCLK, BICK, LRCK) are needed to operate ADC. When PMADC bit is changed to "1", each AIN pin is biased to VCOM voltage. Rising time constant is determined by input capacitor for AC coupling and input resistance. In case of AINL2/AINR2 and 1F input capacitor, time constant is = 1F x 12.5k = 12.5ms (typ) (6) The analog part of ADC is initialized during 2081/fs(=47ms@fs=44.1kHz) after exiting the power-down state. SDTO is "L" at that time. (7) Digital output corresponding to analog input has the group delay (GD) of 17.0/fs(=385s@fs=44.1kHz). (1) (2) (3) (4) (5)
MS0292-E-01 - 22 -
2005/07
ASAHI KASEI 2) DAC HP-amp
[AK4569]
Power supply voltage for headphone amp is supplied from HVDD pin and centered on VCOM. Load resistance of headphone output is min.20. When PMHPL and PMHPR bit are "0", headphone amplifiers are powered-down perfectly. Then HPL and HPR pins are fixed to "L" (HVSS) and a capacitor of MUTET pin works to avoid pop noise.
Power Supply PDN pin (2) >0 PMVCM bit Don't care Clock Input (3) >0 PMDAC bit DAC Internal State SDTI pin PMHPL/R bit HPLMT, HPRMT bit ATTL/R7-0 bit 00H(MUTE) (7) GD (5) HPL/R pin FFH(0dB) (8) 1061/fs (7) (8) (6) (5) 00H(MUTE) FFH(0dB) (7) (8) 00H(MUTE) (7) (8) (6) PD Normal Operation PD Normal Operation PD (4) Don't care (1) >150ns (9)
Figure 18. Power-up/down sequence of DAC and HP-amp (1) PDN pin should be set to "H" at least 150ns after the power is supplied. (2) HPLMT, HPRMT and PMVCM bits should be changed to "1" after PDN pin goes to "H". (3) PMDAC, PMHPL, PMHPR bits should be changed to "1" and HPLMT, HPRMT bits should be changed to "0" after HPLMT, HPRMT, PMVCM bits are changed to "1". Once PMHPL and PMHPR bits are changed to "1", HPLMT and HPRMT bits should be inverted from PMHPL and PMHPR bits respectively. (4) External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC bit = "0", these clocks can be stopped. Headphone amp can operate without these clocks. (5) Rise time of headphone amp is determined by external capacitor of MUTET pin. When C=1F, Rise Time Constant of Headphone Amp: = 100ms (6) Fall time of headphone amp is determined by output capacitor for AC coupling. When C=100F, Fall Time Constant of Headphone Amp: = 200ms (7) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381s@fs=44.1kHz). (8) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (9) Power supply should be switched off after headphone amp is powered down (HPL/R pins become "L").
MS0292-E-01 - 23 -
2005/07
ASAHI KASEI 3) DAC MOUT
Power Supply (1) >150ns PDN pin HPLMT, HPRMT bit PMVCM bit (4) Clock Input Don't care (2) >0 Don't care
[AK4569]
PMDAC bit DAC Internal State SDTI pin PMMO bit ATTL/R7-0 bit
(3) >0 PD(Power-down) Normal Operation PD Normal Operation
00H(MUTE)
FFH(0dB)
00H(MUTE)
FFH(0dB)
MMUTE, ATTM3-0 bit
10H(MUTE) (6) GD (7) 1061/fs (6) (7)
0FH(0dB) (6) (5) (Hi-Z) (5) (7)
MOUT pin
(Hi-Z)
(5)
Figure 19. Power-up/down sequence of DAC and MOUT PDN pin should be set to "H" at least 150ns after the power is supplied. HPLMT, HPRMT and PMVCM bits should be changed to "1" after PDN pin goes to "H". PMDAC and PMMO bits should be changed to "1" after HPLMT, HPRMT and PMVCM bits are changed to "1". External clocks (MCLK, BICK, LRCK) are needed to operate DAC. When PMDAC= "0", these clocks can be stopped. MOUT buffer can operate without these clocks. (5) When PMMO bit is changed to "1", pop noise is output from MOUT pin. (6) Analog output corresponding to digital input has the group delay (GD) of 16.8/fs(=381s@fs=44.1kHz). (7) ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (1) (2) (3) (4)
MS0292-E-01 - 24 -
2005/07
ASAHI KASEI 4) LIN/RIN/MIN HP-amp, MOUT
Power Supply (1) >150ns PDN pin (2) >0 PMVCM bit (3) >0 PMHPL/R bit, PMMO bit HPLMT, HPRMT bit (4) LIN/RIN/MIN pin (Hi-Z) (5) HPL/R pin MMUTE, ATTM3-0 bit (6) (5) (Hi-Z) Don't care
[AK4569]
10H(MUTE) (Hi-Z) (7)
0FH(0dB) (7) (Hi-Z) (7)
MOUT pin
Figure 20. Power-up/down sequence of LIN/RIN/MIN, HP-amp and MOUT (1) PDN pin should be set to "H" at least 150ns after the power is supplied. (2) HPLMT, HPRMT and PMVCM bits should be changed to "1" after PDN pin goes to "H". (3) PMHPL, PMHPR, PMMO bits should be changed to "1" and HPLMT, HPRMT bits should be changed to "0" after HPLMT, HPRMT, PMVCM bits are changed to "1". Once PMHPL and PMHPR bits are changed to "1", HPLMT and HPRMT bits should be inverted from PMHPL and PMHPR bits respectively. (4) When PMHPL, PMHPR or PMMO bit is changed to "1", LIN, RIN and MIN are biased to VCOM voltage. Rising time constant is determined by input capacitor for AC coupling and input resistance 50k (typ). In case of 0.1F input capacitor, time constant is = 0.1F x 50k = 5ms (typ) (5) Rise time of headphone amp is determined by external capacitor of MUTET pin. When C=1F, Rise Time Constant of Headphone Amp: = 100ms (6) Fall time of headphone amp is determined by output capacitor for AC coupling. When C=100F, Fall Time Constant of Headphone Amp: = 200ms (7) When PMMO bit is changed to "1", pop noise is output from MOUT pin.
MS0292-E-01 - 25 -
2005/07
ASAHI KASEI
[AK4569]
Serial Control Interface
Internal registers may be written via to the 3 wire P interface pins (CSN, CCLK and CDTI). The data on this interface consists of Chip address (2bits, Fixed to "10"), Read/Write (1bit, Fixed to "1", Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The value of internal registers is initialized at PDN= "L".
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (Fixed to "10") R/W: Read/Write (Fixed to "1" : Write only) A4-A0: Register Address D7-D0: Control Data Figure 21. Control Interface
MS0292-E-01 - 26 -
2005/07
ASAHI KASEI
[AK4569]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH Register Name Power Management Input Select Timer Select ALC Mode Control 1 ALC Mode Control 2 IPGA Control Mode Control DAC Control Output Select 0 Output Select 1 DAC Lch ATT DAC Rch ATT MOUT ATT D7
HPRMT
D6
HPLMT
0 0 0 0 0
MCKAC
0 0 0 REF6 IPGA6
MCKPD
D5 PMMO 0 ZTM1 ALC REF5 IPGA5 0
SMUTE
D4
PMHPR
D3
PMHPL
D2
PMDAC
D1
PMADC
D0
PMVCM
ADM ZTM0
ZELMN
INR2 WTM1
LMAT1
INR1 WTM0
LMAT0
REF4 IPGA4 ATS
DATTC
TM1 0 0 ATTL7 ATTR7 0
TM0 0 0 ATTL6 ATTR6 0
MINR 0 ATTL5 ATTR5 0
RINR 0 ATTL4 ATTR4
MMUTE
REF3 IPGA3 HPM BST1 DACR MINM ATTL3 ATTR3
ATTM3
REF2 IPGA2 DIF1 BST0 MINL RINM ATTL2 ATTR2
ATTM2
INL2 LTM1 RATT REF1 IPGA1 DIF0 DEM1 LINL LINM ATTL1 ATTR1
ATTM1
INL1 LTM0 LMTH REF0 IPGA0 DFS DEM0 DACL DACM ATTL0 ATTR0
ATTM0
All registers inhibit writing at PDN pin = "L". Note: Unused bits must contain a "0" value. Note: For addresses from 0DH to 1FH, data must not be written.
MS0292-E-01 - 27 -
2005/07
ASAHI KASEI
[AK4569]
Register Definitions
Addr 00H Register Name Power Management Default D7
HPRMT
D6
HPLMT
0
0
D5 PMMO 0
D4
PMHPR
D3
PMHPL
D2
PMDAC
D1
PMADC
D0
PMVCM
0
0
0
0
0
PMVCM: Power Management for VCOM Block 0: Power OFF (Default) 1: Power ON PMADC: Power Management for IPGA and ADC Blocks 0: Power OFF (Default) 1: Power ON MCLK should be present when PMADC bit= "1". PMDAC: Power Management for DAC Blocks 0: Power OFF (Default) 1: Power ON When PMDAC bit is changed from "0" to "1", DAC is powered-up to the current register values (ATT value, sampling rate, etc). PMHPL: Power Management for Lch of Headphone Amp 0: Power OFF (Default). HPL pin becomes HVSS(0V). 1: Power ON PMHPR: Power Management for Rch of Headphone Amp 0: Power OFF (Default). HPR pin becomes HVSS(0V). 1: Power ON PMMO: Power Management for Mono Output 0: Power OFF (Default) MOUT pin becomes Hi-Z. 1: Power ON HPLMT: Mute for Lch of Headphone Amp 0: Normal operation (Default). MUTET pin is connected to VCOM pin internally. 1: Mute. MUTET pin is connected to HPL pin internally. HPLMT: Mute for Rch of Headphone Amp 0: Normal operation (Default). MUTET pin is connected to VCOM pin internally. 1: Mute. MUTET pin is connected to HPR pin internally. HPLMT HPRMT MUTET 0 0 Connected to VCOM 0 1 Connected to HPR 1 0 Connected to HPL 1 1 Connected to HPL,HPR Table 5. MUTET internal connection All blocks can be powered-down by setting the PDN pin to "L" regardless of register values setup. In this case, all control register values are initialized.
MS0292-E-01 - 28 -
2005/07
ASAHI KASEI
[AK4569]
Addr 01H
Register Name Input Select Default
D7 0 0
D6 0 0
D5 0 0
D4 ADM 0
D3 INR2 0
D2 INR1 1
D1 INL2 0
D0 INL1 1
INL2-1: Select ON/OFF of IPGA Lch input. 0: OFF 1: ON Default: INL2=0, INL1=1 INR2-1: Select ON/OFF of IPGA Rch input. 0: OFF 1: ON Default: INR2=0, INR1=1 ADM: Mono Recording Mode 0: Stereo (Default) 1: MONO When ADM= "1", input signal to AINL1 or AINL2 pin is input to both Lch and Rch of ADC.
MS0292-E-01 - 29 -
2005/07
ASAHI KASEI
[AK4569]
Addr 02H
Register Name Timer Select Default
D7 0 0
D6 0 0
D5 ZTM1 0
D4 ZTM0 0
D3 WTM1 0
D2 WTM0 0
D1 LTM1 0
D0 LTM0 0
LTM1-0: ALC limiter operation period (Table 6) When zero crossing is disabled (ZELMN = "1"), the IPGA value is changed immediately by ALC limiter operation. When the IPGA value is changed continuously, the change is done by the period specified by LTM1-0 bits. Default: "00". LTM1 0 0 1 1 ALC Limiter Operation Period 8kHz 16kHz 44.1kHz 0 0.5/fs Default 63s 31s 11s 1 1/fs 125s 63s 23s 0 2/fs 250s 125s 45s 1 4/fs 500s 250s 91s Table 6. ALC Limiter Operation Period at zero crossing disable (ZELMN bit= "1") LTM0
WTM1-0: ALC Recovery Waiting Period (Table 7) WTM1-0 bits set the recovery operation period when any limiter operation does not occur during an ALC operation. Default: "00". WTM1 0 0 1 1 WTM0 0 1 0 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 7. ALC Recovery Operation Waiting Period
Default
ZTM1-0: ALC Zero Crossing Timeout Period (Table 8) When IPGA output detects zero crossing or timeout, the IPGA value is changed by a P WRITE operation, ALC recovery operation, or ALC limiter operation. Default: "00". ZTM1 0 0 1 1 ZTM0 0 1 0 1 Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 8. Zero Crossing Timeout Period
Default
MS0292-E-01 - 30 -
2005/07
ASAHI KASEI
[AK4569]
Addr 03H
Register Name ALC Mode Control 1 Default
D7 0 0
D6 0 0
D5 ALC 0
D4
ZELMN
D3
LMAT1
D2
LMAT0
0
0
0
D1 RATT 0
D0 LMTH 0
LMTH: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 9) LMTH 0 1 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level ADC Input -6.0dBFS -6.0dBFS > ADC Input -8.0dBFS ADC Input -4.0dBFS -4.0dBFS > ADC Input -6.0dBFS Table 9. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
Default
RATT: ALC Recovery GAIN Step (Table 10) During the ALC recovery operation, the number of steps changed from the current IPGA value is set. For example, when the current IPGA value is 3FH, RATT = "1" is set, the IPGA changes to 41H due to the ALC recovery operation, the output signal level is gained by 1dB (=0.5dB x 2). When the IPGA value exceeds the reference level (REF6-0 bits), the IPGA value does not increase. RATT GAIN STEP 0 1 Default 1 2 Table 10. ALC Recovery Gain Step Setting LMAT1-0: ALC Limiter ATT Step (Table 11) During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by LMTH bit, LMAT1-0 bits set the number of steps attenuated from the current IPGA value. For example, when the current IPGA value is 3FH when LMAT1-0 bit = "11", the IPGA value changes to 3BH by the ALC limiter operation, the input signal level is attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA = "00H" (Mute), it clips to "00H". LMAT1 LMAT0 ATT STEP 0 0 1 Default 0 1 2 1 0 3 1 1 4 Table 11. ALC Limiter ATT Step Setting ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (Default) 1: Disable In case of ZELMN = "0", when IPGA output detects zero crossing or timeout, the IPGA value is changed by the ALC operation. Zero crossing timeout is the same as ALC recovery operation. In case of ZELMN = "1", the IPGA value is changed immediately. ALC: ALC Enable Flag 0: ALC Disable (Default) 1: ALC Enable ALC is enabled at ALC bit is "1". Default: "0" (Disable).
MS0292-E-01 - 31 -
2005/07
ASAHI KASEI
[AK4569]
Addr 04H
Register Name ALC Mode Control 2 Default
D7 0 0
D6 REF6 0
D5 REF5 1
D4 REF4 1
D3 REF3 1
D2 REF2 1
D1 REF1 1
D0 REF0 1
REF6-0: Reference Value at ALC Recovery Operation, 0.5dB step, 103 levels, Default: "3FH" (Table 12) During the ALC recovery operation, if the IPGA value exceeds the set reference value by gain operation, IPGA does not become larger than the reference value. For example, when REF= "40H", RATT= "1" (2 step) and IPGA= "3FH", then IPGA is going to become 3FH + 2step = 41H, but IPGA becomes 40H in fact, since REF=40H. GAIN AINL1, AINR1 AINL2, AINR2 (LINE IN) (MIC IN) 67H +20.0dB +32.0dB 66H +19.5dB +31.5dB 65H +19.0dB +31.0dB : : : 3FH 0dB +12.0dB Default : : : 27H 0dB -12.0dB : : : 02H -30.5dB -18.5dB 01H -31.0dB -19.0dB 00H MUTE (-) MUTE (-) Table 12. Reference Value Setting at ALC Recovery Operation DATA
Addr 05H
Register Name IPGA Control Default
D7 0 0
D6 IPGA6 0
D5 IPGA5 1
D4 IPGA4 1
D3 IPGA3 1
D2 IPGA2 1
D1 IPGA1 1
D0 IPGA0 1
IPGA6-0: Input Analog PGA, 0.5dB step, 103 levels, Default: "3FH" (Table 13) When IPGA gain is changed, IPGA6-0 bits should be written while PMADC bit is "1" and ALC bit is "0". IPGA gain is reset when PMADC bit is "0", and then IPGA operation starts from the default value when PMADC is changed to "1". When ALC bit is changed from "1" to "0", IPGA holds the last gain value set by ALC operation. GAIN AINL1, AINR1 AINL2, AINR2 (LINE IN) (MIC IN) +20.0dB +32.0dB +19.5dB +31.5dB +19.0dB +31.0dB : : 0dB +12.0dB : : 0dB -12.0dB : : -30.5dB -18.5dB -31.0dB -19.0dB MUTE (-) MUTE (-) Table 13. Input Gain Setting
DATA 67H 66H 65H : 3FH : 27H : 02H 01H 00H
Default
MS0292-E-01 - 32 -
2005/07
ASAHI KASEI
[AK4569]
Addr 06H
Register Name Mode Control Default
D7
MCKAC
D6
MCKPD
0
0
D5 0 0
D4 ATS 0
D3 HPM 0
D2 DIF1 1
D1 DIF0 0
D0 DFS 0
DFS: Sampling Speed Mode Select (Table 2) DIF1-0: Audio Data Interface Format Default: "10" (Mode 2) HPM: Mono Output Select of Headphone 0: Normal Operation (Default) 1: Mono. (L+R)/2 signals from the DAC are output to both Lch and Rch of headphone. Setting of HPM bit is enabled only at DACL=DACR= "1". DACL 0 1 HPM x 0 1 HPL pin Output No output from DAC Output from Lch of DAC Output (L+R)/2 from DAC
Default
Table 14. Mono Output Select of Headphone (Note. Rch is same.) ATS: Digital attenuator transition time setting (Table 15) ATS 0 1 ATT speed 0dB to MUTE 1 step 1061/fs 4/fs 7424/fs 29/fs
Default
Table 15. Transition time between set values of ATT7-0 bits MCKPD: MCLK Input Buffer Control 0: Enable (Default) 1: Disable When MCLK input with AC coupling is stopped, MCKPD bit should be set to "1". MCKAC: MCLK Input Mode Select 0: CMOS input (Default) 1: AC coupling input
MS0292-E-01 - 33 -
2005/07
ASAHI KASEI
[AK4569]
Addr 07H
Register Name DAC Control Default
D7 TM1 0
D6 TM0 0
D5
SMUTE
D4
DATTC
0
0
D3 BST1 0
D2 BST0 0
D1 DEM1 0
D0 DEM0 1
DEM1-0: De-emphasis Filter Frequency Select DEM1 DEM0 De-emphasis 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz Table 16. De-emphasis Filter Frequency Select BST1-0: Low Frequency Boost Function Select BST1 BST0 BOOST 0 0 OFF Default 0 1 MIN 1 0 MID 1 1 MAX Table 17. Low Frequency Boost Select DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (Default) 1: Dependent At DATTC= "1", ATTL7-0 bits control both Lch and Rch attenuation level, while register values of ATTL7-0 bits are not written to ATTR7-0 bits. At DATTC= "0", ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level. SMUTE: Soft Mute Control 0: Normal operation (Default) 1: DAC outputs soft-muted TM1-0: Soft Mute Time Select TM1 0 0 1 1 TM0 Cycle 0 1024/fs Default 1 512/fs 0 256/fs 1 128/fs Table 18. Soft Mute Time Setting
MS0292-E-01 - 34 -
2005/07
ASAHI KASEI
[AK4569]
Addr 08H
Register Name Output Select 0 Default
D7 0 0
D6 0 0
D5 MINR 0
D4 RINR 0
D3 DACR 0
D2 MINL 0
D1 LINL 0
D0 DACL 0
DACL: DAC Lch output signal is added to Lch of headphone amp. 0: OFF (Default) 1: ON LINL: Input signal to LIN pin is added to Lch of headphone amp. 0: OFF (Default) 1: ON MINL: Input signal to MIN pin is added to Lch of headphone amp. 0: OFF (Default) 1: ON DACR: DAC Rch output signal is added to Rch of headphone amp. 0: OFF (Default) 1: ON RINR: Input signal to RIN pin is added to Rch of headphone amp. 0: OFF (Default) 1: ON MINR: Input signal to MIN pin is added to Rch of headphone amp. 0: OFF (Default) 1: ON
R
LIN/RIN pin
LINL/RINR bit R R MINL/MINR bit R
MIN pin
DACL/DACR
DACL/DACR bit
+ HP-Amp
HPL/HPR pin
Figure 22. Summation circuit for headphone amp output At HPM=0, gain of summation is 0dB for all input path.
MS0292-E-01 - 35 -
2005/07
ASAHI KASEI
[AK4569]
Addr 09H
Register Name Output Select 1 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 MINM 0
D2 RINM 0
D1 LINM 0
D0 DACM 0
DACM: DAC Lch and Rch outputs are added to MOUT buffer amp. Summation gain is -6dB for each channel. 0: OFF (Default) 1: ON LINM: Input signal to LIN pin is added to MOUT buffer amp. 0: OFF (Default) 1: ON RINM: Input signal to RIN pin is added to MOUT buffer amp. 0: OFF (Default) 1: ON MINM: Input signal to MIN pin is added to MOUT buffer amp. 0: OFF (Default) 1: ON
2R
LIN pin
2R
LINM bit
RIN pin
R RINM bit R
MIN pin
2R MINM bit
DACL
2R
DACR
DACM bit
+
MOUT pin
Figure 23. Summation circuit for MOUT Gain of summation is 0dB for MIN and -6dB for LIN, RIN, DACL and DACR.
MS0292-E-01 - 36 -
2005/07
ASAHI KASEI
[AK4569]
Addr 0AH 0BH
Register Name DAC Lch ATT DAC Rch ATT Default
D7 ATTL7 ATTR7 0
D6 ATTL6 ATTR6 0
D5 ATTL5 ATTR5 0
D4 ATTL4 ATTR4 0
D3 ATTL3 ATTR3 0
D2 ATTL2 ATTR2 0
D1 ATTL1 ATTR1 0
D0 ATTL0 ATTR0 0
ATTL7-0: Setting of the attenuation value of output signal from DACL ATTR7-0: Setting of the attenuation value of output signal from DACR The AK4569 has channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to -127dB or MUTE) of each channel. Digital attenuator is independent of soft mute function. ATTL/R7-0 Attenuation FFH 0dB FEH -0.5dB FDH -1.0dB FCH -1.5dB : : : : 02H -126.5dB 01H -127.0dB 00H Default MUTE (-) Table 19. Digital Volume ATT values
Addr 0CH
Register Name MOUT ATT Default
D7 0 0
D6 0 0
D5 0 0
D4
MMUTE
D3
ATTM3
D2
ATTM2
D1
ATTM1
D0
ATTM0
1
0
0
0
0
ATTM3-0: Analog volume control for MOUT MMUTE: Mute control for MOUT 0: Normal operation. ATTM3-0 bits control attenuation value. 1: Mute. ATTM3-0 bits are ignored. (Default) MMUTE ATTM3-0 Attenuation 0FH 0dB 0EH -2dB 0DH -4dB 0CH -6dB : : : : 01H -28dB 00H -30dB x MUTE Table 20. MOUT Volume ATT values
0
1
Default
MS0292-E-01 - 37 -
2005/07
ASAHI KASEI
[AK4569]
SYSTEM DESIGN
Figure 24 shows the system connection diagram. An evaluation board [AKD4569] is available which demonstrates the optimum layout, power supply arrangements and measurement results.
+ 2.2 0.1 0.1 AINL1 28 AINR1 27 AINL2 26 AINR2 25 AVDD 24 AVSS 23 VCOM 22
0.1 VREF 21 LIN 20 +
4.7
1 PDN
P
2 CSN 3 CCLK 4 CDTI 5 LRCK 6 MCLK 7 BICK 8 SDTI 14 HPR
AK4569 Top View
RIN 19 MIN 18 MOUT 17 MUTET 16 HPL 15 13 HVDD 1 6.8 100 Headphone + 16
10 DVDD
9 SDTO
DSP
12 HVSS
11 DVSS
6.8 100 + 16
0.1 0.1
DIR
10
+
10
Digital Ground
Analog Ground
Analog Supply: 2.5 3.6V
Figure 24. Typical Connection Diagram
MS0292-E-01 - 38 -
2005/07
ASAHI KASEI
[AK4569]
1. Grounding and Power Supply Decoupling
The AK4569 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10 resistor. Alternatively if AVDD, DVDD and HVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and HVSS must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4569 as possible, with the small value ceramic capacitors being the nearest.
2. Internal Voltage Reference
Internal voltage reference is output on the VREF pin (typ. 2.1V). An electrolytic capacitor 4.7F in parallel with a 0.1F ceramic capacitor is attached between VREF and AVSS to eliminate the effects of high frequency noise. VCOM is 1.25V(typ) and is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor should be connected between VCOM and AVSS to eliminate the effects of high frequency noise. A ceramic capacitor should be connected to VCOM pin and located as close as possible to the AK4569. No load current may be drawn from VREF and VCOM pins. All signals, especially clocks, should be kept away from the VCOM and VREF pins in order to avoid unwanted coupling into the AK4569.
3. Analog Inputs
The analog inputs are single-ended and the input resistance 50k (typ) for AINL1/AINR1 pins and 12.5k (typ) for AINL2/AINR2 pins. The input signal range is 1.5Vpp centered on VCOM voltage. Usually, the input signal cuts DC with a capacitor. The cut-off frequency is fc=(1/2RC). The AK4569 can accept input voltages from AVSS to AVDD. The ADC output data format is 2's complement. The ADC's DC offset is removed by the internal HPF (fc=3.4Hz@fs=44.1kHz).
4. Analog Outputs
The analog outputs are single-ended outputs and 1.5Vpp(typ) centered on the VCOM voltage. The input data format is 2's compliment. The output voltage is a positive full scale for 7FFFFH(@20bit) and negative full scale for 80000H(@20bit). The ideal output is VCOM voltage for 00000H(@20bit). If the noise generated by the delta-sigma modulator beyond the audio band causes problems, attenuation by an external filter is required. DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM plus a few mV.
MS0292-E-01 - 39 -
2005/07
ASAHI KASEI
[AK4569]
Application Circuit Example
AVDD DVDD
VREF VCOM
VREF VCOM
AK4569
IPGA & ADC
AINL1 AINL2 IPGA MCLK ADC MCKO HPF BICK AINR1 AINR2
HP-amp DAC
AK4116
RX S/PDIF
BICK
XTI
Audio I/F Controller
LRCK LRCK SDTO DAUX SDTO CSN CCLK CDTI
HPL HP-Amp HPR DAC BOOST DATT
SDTI
CDTO
MOUT
MOUT
DSP
BICK CLKOUT
LIN RIN MIN HVDD HVSS MUTET Control Register PDN CSN CCLK CDTI
LRCK SDTI SDTO
AVSS
DVSS
uP
Figure 25. Application Circuit Example
MS0292-E-01 - 40 -
2005/07
ASAHI KASEI
[AK4569]
1) Analog Recording
AVDD DVDD
VREF VCOM
VREF VCOM
AK4569
IPGA & ADC
AINL1 AINL2 IPGA MCLK ADC MCKO HPF BICK AINR1 AINR2
HP-amp DAC
AK4116
RX
BICK
XTI
Audio I/F Controller
LRCK LRCK SDTO DAUX SDTO CSN CCLK CDTI
HPL HP-Amp HPR DAC BOOST DATT
SDTI
CDTO
MOUT
MOUT
DSP
BICK CLKOUT
LIN RIN MIN HVDD HVSS MUTET Control Register PDN CSN CCLK CDTI
LRCK SDTI SDTO
AVSS
DVSS
uP
Figure 26. Clock and Data Flow during Analog Recording (with DAC monitor)
MS0292-E-01 - 41 -
2005/07
ASAHI KASEI
[AK4569]
2) Digital Recording
AVDD DVDD
VREF VCOM
VREF VCOM
AK4569
IPGA & ADC
AINL1 AINL2 IPGA MCLK ADC MCKO HPF BICK AINR1 AINR2
HP-amp DAC
AK4116
RX S/PDIF
BICK
XTI
Audio I/F Controller
LRCK LRCK SDTO DAUX SDTO CSN CCLK CDTI
HPL HP-Amp HPR DAC BOOST DATT
SDTI
CDTO
MOUT
MOUT
DSP
BICK CLKOUT
LIN RIN MIN HVDD HVSS MUTET Control Register PDN CSN CCLK CDTI
LRCK SDTI SDTO
AVSS
DVSS
uP
Figure 27. Clock and Data Flow during Digital Recording (with DAC monitor)
MS0292-E-01 - 42 -
2005/07
ASAHI KASEI
[AK4569]
3) Playback
AVDD DVDD
VREF VCOM
VREF VCOM
AK4569
IPGA & ADC
AINL1 AINL2 IPGA MCLK ADC MCKO HPF BICK AINR1 AINR2
HP-amp DAC
AK4116
RX
BICK
XTI
Audio I/F Controller
LRCK LRCK SDTO DAUX SDTO CSN CCLK CDTI
HPL HP-Amp HPR DAC BOOST DATT
SDTI
CDTO
MOUT
MOUT
DSP
BICK CLKOUT
LIN RIN MIN HVDD HVSS MUTET Control Register PDN CSN CCLK CDTI
LRCK SDTI SDTO
AVSS
DVSS
uP
Figure 28. Clock and Data Flow during Playback
MS0292-E-01 - 43 -
2005/07
ASAHI KASEI
[AK4569]
PACKAGE
28pin QFN (Unit: mm)
0. 2
-C 0. 6
5.2 0.20 5.0 0.10 28 22 1 21
0.60 0.10 22 21 45
+ 0 - 0 .10 .2 0
4
28
0. 2
5
0.
10
1 45
5.2 0.20 5.0 0.10
7 8 0.22 0.05 14 0.50
15
15 14 8
7
0.05 M
0.78 + 0.17
0.80 + 0.20
- 0.28
0.21 0.05
0.02 + 0.03
0.05
Note: The black parts of back package should be open.
Package & Lead frame material
Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
MS0292-E-01 - 44 -
- 0.02
- 0.00
2005/07
ASAHI KASEI
[AK4569]
MARKING
4569
XXXX
1
XXXX : Date code identifier (4 digits)
Revision History
Date (YY/MM/DD) 04/02/20 05/07/19 Revision 00 01 Reason First Edition Error correct Page 21 38-43 45 Contents Bass Boost Function Figure 16: "AK4566" "AK4569" System Design Figures 24 to 28: "AK4566" "AK4569" Marking "4566" "4569"
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0292-E-01 - 45 -
2005/07

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